Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One such FPGA is the Xilinx Virtex® FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Notably, as used herein, “include” and “including” mean including without limitation.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
Heretofore, PLDs have been used to instantiate a design in programmable logic generally for low-volume markets. Low-volume markets conventionally are thought to be greater than two million units per year, and more generally thought to involve sales of five or more million units per year. For high volume markets, Application Specific Integrated Circuits (“ASICs”) were used. However, the time to market for ASICs is slower than for a design instantiated in a PLD. To address higher volume markets with respect to FPGAs, others have suggested forming structured Application Specific Integrated Circuits (“ASICs”), such as HardCopy from Altera of San Jose, Calif. However, such structured ASICs have cost limitations with respect to commercial viability in higher-volume markets.
Accordingly, it would be desirable and useful to provide an ASIC or ASIC-like device for high volume markets with a time to market closer to that of a design instantiated in a PLD and at a lower cost than prior structured ASICs.